Cell design for boundary-scan implementation

This paper gives a new approach in cell design for boundary-scan implementation. After recalling on major problems in PCBs testing, a short overview of boundary-scan standard is given. Furthermore, logic level synthesis of boundary-scan cells are done. Logic level design of these cells are used for layout generation. From generated layout, netlist for each circuit is extracted, and after that simulated by Alecsis2.4. The simulation results are compared with expected values, and are presented in appropriate manner.