Title :
A 3.3 V, 12b, 50MSample/s A/D converter in 0.6 /spl mu/m CMOS with over 80 dB SFDR
Author :
Hui Pan;M. Segami;M. Choi; Jing Cao;F. Hatori;A. Abidi
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
fDate :
6/22/1905 12:00:00 AM
Abstract :
Modern wireless base stations digitize the entire received frequency band, and separate individual channels with digital filters. This requires an A/D converter (ADC) with an effective resolution bandwidth of 20 MHz or more, and a spurious-free dynamic range (SFDR) greater than 85 dB to avoid confusion of a weak received channel with spurious tones. To date, only bipolar ADCs have met these specifications. This high-SFDR wideband ADC implemented in 0.6 /spl mu/m CMOS on a 3M1P epi substrate requires no trimming, calibration or dithering.
Keywords :
"Switches","Frequency","Capacitors","Voltage","Bandwidth","Nonlinear distortion","Operational amplifiers","Circuits","Quantization","MOS devices"
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839682