• DocumentCode
    3783152
  • Title

    The evolution of DSP architectures: towards parallelism exploitation

  • Author

    R. Sernec;M. Zajc;J. Tasic

  • Author_Institution
    IPS, Ljublana, Slovenia
  • Volume
    2
  • fYear
    2000
  • Firstpage
    782
  • Abstract
    This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.
  • Keywords
    "Digital signal processing","Parallel processing","VLIW","Data mining","Arithmetic","Signal processing algorithms","Equations","Digital signal processors","Convolution","Finite impulse response filter"
  • Publisher
    ieee
  • Conference_Titel
    Electrotechnical Conference, 2000. MELECON 2000. 10th Mediterranean
  • Print_ISBN
    0-7803-6290-X
  • Type

    conf

  • DOI
    10.1109/MELCON.2000.880050
  • Filename
    880050
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3783152