Parallel genetic algorithm for optimizing run-time reconfigurable circuits

In this paper a methodology for finding the maximal common subgraph of two directed graphs with parallel genetic algorithm is discussed. The method is directly applicable to the optimization of configurations of FPGA (field programmable gate array) circuits in run-time reconfigurable systems. The problem of finding the maximal common subgraph is known to be NP-complete. The advantage of our approach is that we find optimal or near-optimal solutions in polynomial time using a genetic algorithm. Since the cost function of the optimization task is multimodal, an implementation of the parallel genetic algorithm assures significant improvements of the results.