Achieving multigauge behavior in bit-serial SIMD architectures via emulation

It is shown that the expected benefits of multigauging can be attained without any hardware modification and that additional advantages may be gained from enabling emulations. The authors start with a (physical) bit-serial architecture and build (software) support for multigauge computation on top of its native instruction set. Assumptions about this instruction set are modest and confined solely to its functionality, not its implementation. Multigauge behavior is achieved as a high-level abstraction, which is independent of the physical design. The danger that (hardware-enabled) multigauge behavior might preclude certain types of hardware optimization is avoided.