The IEEE rounding for multiplier with redundant operands

We present a design for a multiplier with redundant operands which conforms to the IEEE-754 floating-point standard. The design consists of a multiplier core and a rounding unit which conforms to the rounding modes specified by the IEEE standard and introduces a novel technique for calculating the sticky bit directly from the operands. We simulate a single-extended precision design and evaluate the delay versus a conventional design to be roughly equivalent, with extra savings possible with minor modification. The area is also estimated to be roughly 15% larger than a conventional design of the same precision.