A sampled-analog rank-order-filter architecture

We propose a sampled-analog rank-order filter (ROF) architecture of complexity O(n/sup 2/). It yields a very compact structure because the devices used are essentially of minimum geometry. Its sole active building block being the simple CMOS inverter, the circuit exhibits an excellent low-voltage compatibility. Furthermore, it can support a rail-to-rail input range. It is inherently fast due to the fully parallel signal processing, and the speed is expected to increase with technological scaling at the same rate as purely digital circuitry. Finally, it supports full programmability of the rank by means of an analog reference voltage. The ROF is based on a pair of multiple-winners-take-all (mWTA) circuits and a set of AND gates. The paper includes a description of the architecture and a detailed analysis of the mWTA. Most relevant design issues are addressed, and experimental results obtained from a fabricated ROF are presented.