High-speed CRC computation using state-space transformations

Parallelization of the linear-feedback shift register used to compute the CRC has long been recognized as a way to increase throughput. In all applications of this technique reported previously, the achievable increase in throughput is limited by an increase in the circuit complexity within the feedback loop; for a circuit that processes M bits of the input sequence in parallel, the throughput increase, or speed-up, appears to be asymptotically limited to M/2. In this paper, we develop a state-space transformation for the M-bits-at-a-time CRC system that reduces the complexity of its feedback loop to exactly that of the original bit-at-a-time system. This simplification comes at the cost of increased circuit complexity outside the feedback loop; however, these blocks can be pipelined. Thus the transformed system can achieve a full speed-up factor of M compared to the bit-at-a-time system. The transformation introduced in this paper is general in that it is valid in any field. It can thus be applied to encoders for cyclic codes over arbitrary finite fields that process M elements of an input sequence in parallel.