Title :
On signal-gating schemes for low-power adders
Author :
Zhijun Huang;M.D. Ercegovac
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
Signal gating schemes for low-power adder design are studied in this paper. Signal gating dynamically deactivates portions of an adder according to the actual precision of two operands. Based on program analysis, signal gating is developed for two different adders: symmetric adders and asymmetric adders. The effect of signal gating is investigated by incorporating several gating schemes into a RISC pipeline. Experimental results indicate more power saving compared to previous work.
Keywords :
"Adders","Pipelines","Arithmetic","Logic","Computer science","Signal design","Signal analysis","Reduced instruction set computing","Energy consumption","Circuits"
Conference_Titel :
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Print_ISBN :
0-7803-7147-X
DOI :
10.1109/ACSSC.2001.987047
