Phase synchronization using zero crossing sampling digital phase-locked loop

The main objective of this paper is to analyze a zero crossing sampling digital phase-locked loop (PLL) as a building block for a phase synchronization system. To that purpose, the paper deals with modeling, analysis and implementation issues of the PLL. Derived are nonlinear and linear state-space models and a transfer function model. Operation of the PLL is also analyzed using frequency domain methods. An implementation of the PLL using a digital signal processor is described. On the basis of the derived models, two different system controllers are designed and the system transient response for the two cases is compared. The first controller is of a proportional-integral (PI) type and the second controller is minimum response time controller. It is shown how the input signal amplitude variations affect the system transient response. A solution for solving this problem is presented.