DocumentCode
3784390
Title
Fast reconstruction of clock-control sequence
Author
W.G. Chambers;J.D. Golic
Author_Institution
Dept. of Electron. Eng., King´s Coll. London, UK
Volume
38
Issue
20
fYear
2002
Firstpage
1174
Lastpage
1175
Abstract
Two fast techniques for reconstructing the initial state of the clock-control shift register in the shrinking generator, one based on list decoding and the other on information set decoding, are investigated. Both start from computing the a posteriori probabilities for the clock-control bits from a known segment of the output sequence, under the assumption that the initial state of the clock-controlled shift register is already recovered.
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020799
Filename
1040980
Link To Document