DocumentCode
378531
Title
An RT-level ATPG based on clustering of circuit states
Author
Li, Huawei ; Min, Yinghua ; Li, Zhongcheng
Author_Institution
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fYear
2001
fDate
2001
Firstpage
213
Lastpage
218
Abstract
This paper introduces a new technique employed in a test generation system, ATCLUB, at RT-level, based on clustering of circuit states. States or some sets of states in a low-level description are mapped to high levels in terms of a particular variable in a behavioral description, and termed behavioral phases. Further clustering of behavioral phases is performed to represent the function of a circuit more explicitly and refinedly. Such a refined representation is then used in the test generation algorithm to simplify and speed up search process of test sequences. Experimental results demonstrate the computational efficiency of the clustering process and test pattern generation
Keywords
VLSI; automatic test pattern generation; hardware description languages; high level synthesis; integrated circuit testing; logic testing; sequential circuits; ATCLUB; RT-level ATPG; VLSI; automatic test pattern generation; behavioral description; behavioral phases; circuit states; clustering; computational efficiency; low-level description; search process; test generation system; Automatic test pattern generation; Circuit testing; Clocks; Clustering algorithms; Genetic algorithms; Hardware design languages; Lighting control; Sequential circuits; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location
Kyoto
ISSN
1081-7735
Print_ISBN
0-7695-1378-6
Type
conf
DOI
10.1109/ATS.2001.990284
Filename
990284
Link To Document