Distance constrained dimensionality reduction for parametric fault test generator

Measurement of Parametric specifications like delay, power, gain, etc., is difficult, expensive and require specialized test instrumentation, as they are essentially analog in nature. Due to these problems, alternate tests are used to implicitly verify parametric specifications. For most nontrivial circuits, alternate test generation is a time-consuming and complex task. In this paper, we utilize a novel technique for fast exploration of the specification space to determine redundancy in specification tests prior to alternate test generation. If significant redundancies exist, a low dimensional embedding is determined to provide a target for the classification method operating on the alternate test measurements. The proposed method uses the same data that is generated by conventional tests, hence requiring minimal additional effort in data collection and can also be used on high dimensional data with complex nonlinear structure