The data acquisition system of the Belle silicon vertex detector (SVD) upgrade

Author

H. Ishino;R. Abe;T. Abe;H. Aihara;Y. Asano;T. Aso;A. Bakich;T. Browder;M.C. Chang;Y. Chao;K.F. Chen;S. Chidzik;J. Dalseno;R. Dowd;J. Dragic;C.W. Everton;R. Fernholz;M. Friedl;H. Fujii;Z.W. Gao;A. Gordon;Y.N. Guo;J. Haba;K. Hara;T. Hara;Y. Harada;T. Haruya

Author_Institution

Dept. of Phys., Tokyo Inst. of Technol., Japan

Volume

51

Issue

5

fYear

2004

Firstpage

2064

Lastpage

2068

Abstract

A newly developed data acquisition system (DAQ) for the upgraded silicon vertex detector (SVD2) in the Belle experiment is described. The system consists of 12 PCs connected through PCI I/O boards to 36 flash analog-to-digital converters (FADCs) to read out a system comprising a total of 110 592 strips. It is designed to cope with the increased number of readout channels and the maximum trigger rate of 1 kHz, foreseen in the future operation with higher beam currents. A measurement of the system performance using sparsification algorithm we have developed yields a 1.3-kHz readout rate for a 5% occupancy with less than 5% dead time, which satisfies the requirements on the maximum trigger rate.

Keywords

"Data acquisition","Silicon","Detectors","Chaos","Personal communication networks","Analog-digital conversion","Strips","Time measurement","System performance"

Journal_Title

IEEE Transactions on Nuclear Science

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2004.832649

Filename

1344285