DocumentCode :
3787371
Title :
The vector-thread architecture
Author :
B. Krashinsky;C. Batten;M. Hampton;S. Gerding;B. Pharris;J. Casper;K. Asanovic
Volume :
24
Issue :
6
fYear :
2004
Firstpage :
84
Lastpage :
90
Abstract :
The vector-thread (VT) architectural paradigm describes a class of architectures that unify the vector and multithreaded execution models. VT architectures compactly encode large amounts of structured parallelism in a form that lets simple microarchitectures attain high performance at low power by avoiding complex control and data path structures and by reducing activity on long wires
Keywords :
"Process control","Computer architecture","Parallel processing","Virtual private networks","Embedded computing","Circuits","Encoding","Registers","Information processing","Cost function"
Journal_Title :
IEEE Micro
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2004.90
Filename :
1388162
Link To Document :
بازگشت