Title :
An 800 Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking
Author :
Yoshikawk, T. ; Yoshida, T. ; Ebuchi, T. ; Arima, Y. ; Iwata, T. ; Nishimura, K. ; Kimura, H. ; Komatsu, Y. ; Yamauchi, H.
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /spl beta/port requires 180 mW active power and is treated as ASIC macro for future large system integration.
Keywords :
IEEE standards; application specific integrated circuits; consumer electronics; large scale integration; local area networks; 0.25 micron; 1.2 km; 180 mW; 800 Mbit/s; ASIC macro; DS-port; IEEE1394-2000; P1394b Draft 1.01; active power; consumer electronics networking; hybrid port architecture; large system integration; peer-to-peer IEEE1394 networking; physical layer LSI; Analog circuits; Clocks; Consumer electronics; Large scale integration; Peer to peer computing; Phase detection; Phase frequency detector; Physical layer; Pipelines; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992945
