DocumentCode :
3787931
Title :
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
Author :
V. Stojanovic;A. Ho;B.W. Garlepp;F. Chen;J. Wei;G. Tsang;E. Alon;R.T. Kollipara;C.W. Werner;J.L. Zerbe;M.A. Horowitz
Author_Institution :
Rambus Inc., Los Altos, CA, USA
Volume :
40
Issue :
4
fYear :
2005
Firstpage :
1012
Lastpage :
1026
Abstract :
This paper describes an adaptively equalized, dual-mode (PAM2 one-tap DFE/PAM4) 0.13 /spl mu/m CMOS transceiver chip, and the techniques used to continuously adapt the link. Interestingly, with only minor modification the same hardware needed to implement a PAM4 system can be used to implement a PAM2 loop-unrolled single-tap decision-feedback equalization (DFE) receiver. Adaptive equalization using data-based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. To allow the transmitter to adapt to the channel, the link uses common-mode signaling to create a back-channel communication path over the existing pair of wires. The design uses a three-level return-to-null signaling scheme which allows the receiver to simultaneously extract voltage and timing references and minimize the required receiver hardware. The measured results indicate that this back-channel achieves reliable communication without noticeable impact on the forward link for back-channel data rates of up to 16 Mb/s and swings of 20-100 mV.
Keywords :
"Transceivers","Adaptive equalizers","Decision feedback equalizers","Hardware","Adaptive filters","Filtering","Costs","Transmitters","Wires","Signal design"
Journal_Title :
IEEE Journal of Solid-State Circuits
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2004.842863
Filename :
1424234
Link To Document :
بازگشت