DocumentCode
378806
Title
The on-chip 3 MB subarray based 3rd level cache on an Itanium microprocessor
Author
Weiss, D. ; Wuu, J.J. ; Chin, V.
Author_Institution
Hewlett-Packard Co., Fort Collins, CO, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
112
Abstract
This 3 MB on-chip level-three cache employs subarray design style, and achieves 85% array efficiency. Characterized to operate up to 1.2 GHz, the cache allows a store and a load in every four core cycles, and provides a total bandwidth of 64 GB/s at 1.0 GHz.
Keywords
cache storage; cellular arrays; microprocessor chips; 1.0 GHz; 1.2 GHz; 3 MB; 64 GB/s; Itanium microprocessor; array efficiency; bandwidth; core cycles; level-three cache; on-chip subarray; subarray design style; Assembly; Circuits; Clocks; Decoding; Microprocessors; Random access memory; Repeaters; Signal generators; Testing; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992964
Filename
992964
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