DocumentCode
378810
Title
A 10 Gb/s and 40 Gb/s forward-error-correction device for optical communications
Author
Leilei Song ; Meng-Lin Yu ; Shaffer, M.S.
Author_Institution
High-Speed Commun. VLSI Res., Agere Syst., Holmdel, NJ, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
128
Abstract
Two forward error-correcting devices for OC-48/192/768 are implemented in 1.5 V 0.6 /spl mu/m CMOS. A 10 Gb/s (or Quad 2.5 Gb/s) device with 424k-gate Reed-Solomon core consumes 343 mW. A 40 Gb/s device contains 364k-gates and consumes 361 mW.
Keywords
CMOS digital integrated circuits; Reed-Solomon codes; decoding; digital communication; forward error correction; interleaved codes; optical communication equipment; 0.6 /spl mu/m CMOS; 0.6 micron; 1.5 V; 10 Gb/s; 10 Gbit/s; 361 mW; 40 Gb/s; 40 Gbit/s; SONET/SDH frames; complexity; error-correcting BCH code; error-correcting Reed-Solomon code; forward-error-correction device; optical communication; power consumption; single-chip solution; Bit error rate; Decoding; Equations; Forward error correction; Hardware; High speed optical techniques; Optical devices; Optical fiber communication; SONET; Synchronous digital hierarchy;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992969
Filename
992969
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