DocumentCode
378814
Title
Low-power small-area /spl plusmn/7.28 ps jitter 1 GHz DLL-based clock generator
Author
Chulwoo Kim ; In-Chul Hwang ; Sung-Mo Kang
Author_Institution
Illinois Univ., Urbana, IL, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
142
Abstract
A 1 GHz DLL-based clock generator in 0.35 /spl mu/m CMOS occupies 0.08 mm/sup 2/. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems. Measured peak-to-peak jitter is /spl plusmn/7.28 ps.
Keywords
CMOS digital integrated circuits; clocks; delay lock loops; frequency multipliers; low-power electronics; phase detectors; timing jitter; 0.35 micron; 1 GHz; 7.28 ps; DLL clock generator; frequency multiplier; low-power small-area CMOS circuit; peak-to-peak jitter; phase detector; reset circuit; Clocks; Delay lines; Design for quality; Frequency conversion; Frequency synthesizers; Jitter; Microelectronics; Microprocessors; Phase locked loops; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992976
Filename
992976
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