DocumentCode
378816
Title
The core clock system on the next generation Itanium/spl trade/ microprocessor
Author
Anderson, F.E. ; Wells, J.S. ; Berta, E.Z.
Author_Institution
Intel Corp., Fort Collins, CO, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
146
Abstract
A PLL generates a high-frequency core clock for a 1GHz processor by multiplying up the system clock. The clock is distributed across the 19/spl times/14 mm/sup 2/ core via a shielded, balanced, H-tree to the final pulsed gated buffers with <62 ps measured skew. Test features include phase shrinking and regional skew manipulation.
Keywords
buffer circuits; clocks; digital phase locked loops; microprocessor chips; 1 GHz; Itanium microprocessor; PLL; core clock system; high-frequency core clock; phase shrinking; pulsed gated buffers; regional skew manipulation; shielded balanced H-tree; skew; Clocks; Delay; Feedback; Frequency synchronization; Inductance; Jitter; Microprocessors; Noise reduction; Phase locked loops; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992978
Filename
992978
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