DocumentCode
378819
Title
A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write
Author
Barth, J. ; Anand, D. ; Dreibelbis, J. ; Nelson, E.
Author_Institution
IBM MicroElectronics, Burlington, VT, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
156
Abstract
A 0.12 /spl mu/m growable eDRAM macro has GND sense, bit-line twisting, direct reference cell write, a flexible multi-banking protocol, and column redundancy to support multi-banking. The protocol supports simultaneous activate, read/write and pre-charge to three different banks. Hardware measurements verify 300 MHz operation, 6.6 ns tacc, and 10 ns trc.
Keywords
DRAM chips; cellular arrays; integrated circuit measurement; protocols; redundancy; reference circuits; 0.12 micron; 10 ns; 300 MHz; 6.6 ns; GND sense; bit-line twisting; column redundancy; direct reference cell write; flexible multi-banking protocol; hardware measurements; multi-banked eDRAM macro; simultaneous activate-read/write-precharge; Application specific integrated circuits; Capacitance; Driver circuits; Logic testing; Microelectronics; Optimized production technology; Random access memory; Region 1; Voltage; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992983
Filename
992983
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