A 43 Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

Author

Nakasha, Y. ; Suzuki, T. ; Kano, H. ; Ohya, A. ; Sawada, K. ; Makiyama, K. ; Takahashi, T. ; Nishi, M. ; Hirose, T. ; Takikawa, M. ; Watanabe, Y.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

190

Abstract

A 43 Gb/s 4:1 multiplexer in 0.13/spl mu/m InP-based HEMT technology contains a 52 Gb/s static D-FF and a phase adjuster giving the D-FF 360/spl deg/ effective phase margin. Microwave techniques and optimization of layout enable 43 Gb/s operation with 43 GHz full-rate clock. Power dissipation is 7.9 W at -5.2 V.

Keywords

III-V semiconductors; circuit optimisation; digital communication; high electron mobility transistors; indium compounds; integrated circuit layout; microwave integrated circuits; multiplexing equipment; optical fibre communication; synchronous digital hierarchy; -5.2 V; 43 GHz; 43 GHz full-rate clock; 43 Gb/s; 43 Gbit/s; 4:1 multiplexer; 5.2 V; InAlAs-InGaAs-InP; InAlAs/InGaAs/InP; InP-based HEMT; chip micrograph; layout optimization; phase adjuster; power dissipation is 7.9 W; Bandwidth; Capacitance; Clocks; Coupling circuits; Frequency conversion; HEMTs; Inductors; Jitter; Multiplexing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993000

Filename

993000