A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Author

Sang-Hyun Lee ; Moon-Sang Hwang ; Youngdon Choi ; Sungjoon Kim ; Yongsam Moon ; Bong-Joon Lee ; Deog-Kyoon Jeong ; Wonchan Kim ; Young June Park ; Gi-Jung Ahn

Author_Institution

Seoul Nat. Univ., South Korea

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

256

Abstract

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

Keywords

CMOS integrated circuits; error statistics; integrated circuit measurement; jitter; optical receivers; signal sampling; synchronisation; 0.25 micron; 5 Gbit/s; BER; CDR; CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit; PRBS; data recovery; eye-measuring loop; jitter conditions; jitter shape; maximum eye-opening; pseudo-random-bit-sequence; variable-interval oversampling clock/data recovery circuit; Bandwidth; Circuits; Clocks; Delay; Frequency; Jitter; Moon; Sampling methods; Silicon; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993033

Filename

993033