Title :
Adaptive supply serial links with sub-1 V operation and per-pin clock recovery
Author :
Jaeha Kim ; Horowitz, M.A.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
Adaptive power-supply regulation is extended to serial links, by using 5:1 multiplexing and low-voltage transceivers for power saving, and by scaling link properties with bit rate, especially in per-pin clock recovery PLL/DLLs. The serial link operates at 0.45-3.5 Gb/s for 0.9-2.5 V supply and dissipates 9.2-197 mW.
Keywords :
delay lock loops; digital communication; multiplexing; phase locked loops; power supply circuits; synchronisation; telecommunication links; transceivers; 0.45 to 3.5 Gbit/s; 0.9 to 2.5 V; 9.2 to 197 mW; adaptive power-supply regulation; adaptive supply serial links; bit rate; link properties scaling; low-voltage transceivers; multiplexing; per-pin clock recovery; per-pin clock recovery DLL; per-pin clock recovery PLL; power dissipation; power saving; serial link operating rate; serial links; Bandwidth; Bit rate; Clocks; Delay; Driver circuits; Frequency; Latches; Phase locked loops; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993039
