A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback

Author

Yamauchi, Hiroyuki ; Okada, Shogo ; Taketa, Koji ; Matsuda, Yuuki ; Mori, Takayoshi ; Okada, Shogo ; Watanabe, Toshio ; Harada, Y. ; Matsudaira, M. ; Matsushita, Yuki

Author_Institution

Sanyo Electr. Co. Ltd., Gifu, Japan

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

372

Abstract

A HDTV video processor with decoding/display of two MPEG MP@HL streams and reverse playback with smooth 30 frames/s without frame skip uses a 0.18 /spl mu/m 5-layer process in 6.86/spl times/6.86 mm/sup 2/ and 5.7M transistors. It is for home multimedia and mobile TV applications. It operates at 135 MHz and 0.8 W at 1.8 V.

Keywords

decoding; digital signal processing chips; high definition television; multimedia communication; television receivers; video coding; 0.18 micron; 0.8 W; 1.8 V; 135 MHz; 6.86 mm; HDTV video processor; MPEG2 MP@HL streams; five-layer process; frame skip; home multimedia applications; mobile TV applications; reverse playback capability; simultaneous decoding; Clocks; Decoding; Digital signal processing; Displays; Engines; Frequency; HDTV; SDRAM; Streaming media; Video recording;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993087

Filename

993087