A 10 /spl mu/V-offset 8 kHz bandwidth 4/sup th/-order chopped /spl Sigma//spl Delta/ A/D converter for battery management

Author

Blanken, P.G. ; Menten, S.E.J.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

388

Abstract

A chopped 4/sup th-/order continuous-time 1 bit /spl Sigma//spl Delta/ A/D converter with 10 /spl mu/V offset and 8 kHz bandwidth has been designed for battery current measurement. Chopping at 16 kHz, the circuit has a 0.1 V input range, a 68 dB SNR, and a 1 MHz output bit rate. Area is 0.45x0.4 mm in 0.35 /spl mu/m CMOS. Current consumption is 30 /spl mu/A at 2.5-4 V.

Keywords

CMOS integrated circuits; analogue-digital conversion; battery testers; choppers (circuits); electric current measurement; reference circuits; sigma-delta modulation; 0.35 micron; 0.4 mm; 0.45 mm; 1 bit; 16 kHz; 2.5 to 4 V; 30 muA; 8 kHz; CMOS; SNR; bandwidth; battery current measurement; chopped fourth-order continuous-time /spl Sigma//spl Delta/ A/D converter; chopping frequency; current consumption; input offset; input voltage range; output bit rate; Bandwidth; Battery charge measurement; Clocks; Current measurement; Feedforward systems; Resistors; Switches; Timing; Transconductors; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993095

Filename

993095