DocumentCode
378901
Title
A fully-bypassed 6-issue integer datapath and register file on an Itanium microprocessor
Author
Fetzer, E.S. ; Orton, J.T.
Author_Institution
Hewlett-Packard Co., Fort Collins, CO, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
420
Abstract
A 6-issue integer datapath with a 20-ported 128/spl times/65 bit register file in a 0.18 /spl mu/m process operates up to 1.2 GHz at 1.5 V. Operands bypass through 4 stages, from 34 locations, using 1/2 clock for execution and 1/2 clock for bypass. Each result is available for the next instruction.
Keywords
computer architecture; digital arithmetic; microprocessor chips; shift registers; 0.18 micron; 1.2 GHz; 1.5 V; 65 bit; Itanium microprocessor; bypass clock cycles; execution clock cycles; fully-bypassed six-issue integer datapath; multi-port register file; operand bypass stages; operand locations; register file; Clocks; Delay; Feedback circuits; Latches; Logic devices; Microprocessors; Radio frequency; Registers; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993111
Filename
993111
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