3789703

Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI"

J.C. Harden;T.E. Mangir

Mississippi State University, Mississippi, MS, USA

74

3

1986

515

516

"Very large scale integration","Yield estimation","Statistics","Equations","Predictive models","Probability","Redundancy"

Proceedings of the IEEE

ieee

0018-9219

jour

10.1109/PROC.1986.13492

1457760