Title :
Framework for synthesis of virtual pipelines
Author :
Dasasathyan, Srinivasan ; Radhakrishnan, Rajesh ; Vemuri, Ranga
Author_Institution :
Dept. of Electron. Comput. & Eng. Comput., Sci., Cincinnati Univ., OH, USA
Abstract :
Virtual pipelining allows designs of arbitrary size to execute on finite sized FPGA devices. It allows pipelined designs to be efficiently configured on an FPGA by overlapping the reconfiguration time of a pipeline stage with the execution time of previous pipeline stages. This technique produces performance improvement up to an order of 5 versus a nonpipelined execution of a design. We extend this principle for handling large designs that were previously too large to fit on an FPGA. This paper presents a framework for automatically synthesizing virtual pipelines on a Virtex FPGA. We also suggest criteria for extending our approach to nonVirtex FPGAs
Keywords :
circuit CAD; field programmable gate arrays; integrated circuit design; logic CAD; logic simulation; parallel architectures; pipeline processing; reconfigurable architectures; FPGA; Virtex FPGA; automatic virtual pipeline synthesis; design execution; finite sized FPGA devices; performance improvement; pipeline stage; pipeline stage execution time; pipelined design configuration; reconfiguration time overlapping; virtual pipeline synthesis framework; virtual pipelining; Contracts; Field programmable gate arrays; Flip-flops; Logic design; Logic devices; Performance loss; Pipeline processing; Reconfigurable logic; Runtime; Throughput;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994943
