Battery-efficient architecture for an 802.11 MAC processor

Rapid growth in the complexity of wireless devices, communication protocols, and applications, combined with slow improvements in battery technologies, have created a "battery gap" that is only projected to increase with advances in wireless communication technologies and applications. Conventional approaches to bridging this gap exploit low-power network protocols and handset architectures. However, it is now well known that minimizing the total energy or average power drawn from a battery does not necessarily lead to maximizing battery life, calling for new battery-driven approaches to protocol and hardware design. We present a battery-efficient architecture for an 802.11 MAC processor, which incorporates a new battery-driven approach to power management. The MAC processor employs a novel on-chip bus architecture that is capable of regulating the profile of the current drawn by the system, enabling battery discharge at high efficiencies. The proposed battery friendly MAC processor architecture enables significant increases in battery capacity and lifetime, while minimizing performance impacts. Further, the developed architecture provides mechanisms that allow for trade-offs between battery life and performance, and can be configured to adapt the power management techniques based on the network traffic characteristics.