On the evaluation of fairness for input queue switches

Packet switches are required to support quality of service (QoS), that is, the capability to differentiate packet servicing on a flow basis, ensuring switching objectives such as guaranteed throughput and bounded switching delays. The core of a packet switch is a switch fabric, which is typically available as a single chip or chip set. Currently, these chip sets do not support QoS features, such as required packet service rates. We develop a framework based on performance indicators for evaluating a packet switch with respect to fairness performance. In conjunction with a robust simulation environment, we analyze the performance of two well known core packet schedulers.