Applying the TIL concept to bipolar power transistors

The results obtained in the implementation of the novel two interdigitation-level (TIL) configuration in 0.14-cm/sup 2/ emitter area, TO-3 packaged, bipolar power n-p-n transistors are reported. It is shown that in comparison with conventional triple-diffused n-p-n transistors of the same class processed simultaneously, the TIL-type devices presented the following advantages: (1) a 25% to 30% increase of voltage rating (V/sub CEO(SUS)/ and V/sub CBO/) at identical (base-line) gain h/sub FE/; (2) an enhanced electrothermal failure safety; (3) a decreased value of the delay t/sub d/, storage t/sub s/, and fall t/sub f/ times; and (4) an increase of the small-signal gain h/sub fe/. The peak switched-collector current density of TIL transistors is in excess of 500 A/cm/sup 2/. A distinct benefit obtained through the implementation of the TIL concept, which offers a fair balance between manufacturability ease/cost effectiveness and overall device performance, is the relaxation of the tradeoff between the doping/width of the p-base and the main electrical parameters of transistors.