A test design method for floating gate defects (FGD) in analog integrated circuits

Author

Pronath, Michael ; Graeb, Helmut ; Antreich, Kurt

Author_Institution

Inst. for Electron. Design Autom., Technische Univ. Munich, Germany

fYear

2002

fDate

2002

Firstpage

78

Lastpage

83

Abstract

A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the sets of undetectable values of the trapped charge on the floating gate transistor It covers all potential gate charges of an FGD at one or more transistors and allows the application of conventional circuit simulators for simulating DC, AC and transient test. Based on this fault simulation, a test design methodology is presented that can determine all test sets that detect all FGDs for all possible values of gate charge

Keywords

CMOS analogue integrated circuits; analogue integrated circuits; circuit simulation; fault simulation; integrated circuit testing; transient analysis; CMOS; FGDs; analog integrated circuits; circuit simulators; fault simulation; floating gate defects; floating gate transistor; simulator output; test design method; test design methodology; transient test; trapped charge; undetectable values; Analog circuits; Analog integrated circuits; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Costs; Design methodology; Integrated circuit testing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998252

Filename

998252