A new design flow and testability measure for the generation of a structural test and BIST for analogue and mixed-signal circuits

For the generation of defect-oriented tests, a system is developed that includes the synthesis of self-test structures. With the objective of generating a highly efficient analogue test, the fault simulation methods are greatly enhanced: (1) a new testability measure, (2) the possibility of distinguishing between not-to-detect and hard-to-detect faults with respect to the tolerances of the respective measurement system. By presenting a new design flow and using the fault simulation in a very early design stage, a tool-suite is developed. It allows one to control the defect-robust layout and to eliminate those faults that limit the efficiency of a measurement system. This allows for economic self-test applications. It is demonstrated that the system finds the most efficient and less expense test for a given fault set. With the presented results it is possible to include the defect-oriented approach from the fault simulation to the automatic generation of layout rules and the test synthesis in an industrial design flow