DocumentCode
379772
Title
The selective pull-up (SP) noise immunity scheme for dynamic circuits
Author
Stan, Mircea R. ; Panigrahi, Avishek
Author_Institution
Virginia Univ., Charlottesville, VA, USA
fYear
2002
fDate
2002
Firstpage
1106
Abstract
Summary form only given. Noise is an important consideration in the design of integrated circuits. Increased immunity to noise, however, typically comes at the expense of increased delay. So, it is very important to have an adequate noise immunity with a minimum penalty in performance. "Global" noise immunity schemes can be used when the noise is approximately the same on all nodes in the circuit; but when a few nodes are noisier then others much better results can be obtained by selective noise immunity schemes. The selective pull-up (SP) technique for dynamic circuits is a method for improving the noise immunity of inputs selectively, so that the least penalty in delay is paid for inputs that intrinsically have higher noise immunity
Keywords
delays; integrated circuit design; integrated circuit noise; logic design; circuit nodes; delay penalty; dynamic circuits; global noise immunity schemes; integrated circuit design; noise immunity; performance penalty; selective noise immunity schemes; selective pull-up noise immunity scheme; Circuit noise; Circuit testing; Delay; Design automation; Integrated circuit noise; Inverters; MOS devices; MOSFETs; Noise level; Space vector pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998462
Filename
998462
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