Finding a common fault response for diagnosis during silicon debug

When a design is manufactured for the first time, it may suffer from timing-related errors that result from inaccuracies in the timing analysi tool used during the design process. Such errors will appear as delay faults in all (or many) of the manufactured chips. In addition, variations that occur during the manufacturing process may cause delay defects that vary across chips. It is necessary to diagnose and correct failures of the first type (in the presence of failures of the second. type) before the chip can be manufactured again. This may have to be repeated until design errors are eliminated. Experiments that enable one to find common fault responses of faulty circuits are described