Design in the Power-Limited Scaling Regime

Technology scaling has entered a new era, where chip performance is constrained by power dissipation. Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings. This paper examines technology options in the power-limited-scaling regime and reviews sensitivity-based analysis that can be used for the optimal selection of optimal architectures and circuit implementations to achieve the best performance under power constraints. These tradeoffs are examined in the context of power minimization at the technology, circuit, logic, and architecture levels, both at the design and run times.