DocumentCode
3807096
Title
Integration of PtSi in p-Type MOSFETs Using a Sacrificial Low-Temperature Germanidation Process
Author
N. Breil;E. Dubois;A. Halimaoui;A. Pouydebasque;A. Laszcz;J. Ratajcak;G. Larrieu;T. Skotnicki
Author_Institution
STMicroelectronics, Crolles
Volume
29
Issue
2
fYear
2008
Firstpage
152
Lastpage
154
Abstract
In this letter, an original selective etching method of Pt with respect to PtSi using a sacrificial low-temperature germanidation process is used for the integration of valence band edge contacts in p-type MOSFET devices. After silicidation annealing, the excess of Pt due to incomplete reaction with silicon or standing on insulating layers can be transformed into the PtGe2 phase. The solubility of this phase in a sulfuric peroxide mixture (SPM) without altering PtSi is demonstrated. The suitability and scalability of the proposed integration scheme is shown through the successful integration and characterization of PtSi source/drain contacts in p-type MOSFETs.
Keywords
"MOSFETs","Silicides","Etching","Annealing","Silicon","Silicidation","Scanning probe microscopy","Insulation","Contact resistance","Chemical technology"
Journal_Title
IEEE Electron Device Letters
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2007.914090
Filename
4435963
Link To Document