Scalable Digital Multiphase Modulator

An architecture is presented for digital multiphase modulators (MPM) that leads to an efficient, high performance hardware realization. The combined modulator, switching phases and output filter are viewed as a multilevel digital-to-analog converter with high power output, or a power D/A, and concepts used in D/A converters are leveraged to achieve high performance and hardware efficiency. The modulator is split into three functional blocks including a decoder that determines how many phases are on at any time, a selector that determines which phases are on at any time, and a single high-resolution module that is time-shared among all phases. The resulting architecture scales favorably with a large number of phases and facilitates fast update rates of the input command well above the single phase-switching frequency, f_s. Experimental results are presented for a custom integrated circuit realization in a 0.35-muCMOS process, designed for 16-phase output with an input command update rate of 16 times f_s. Two complete 16 phase MPM designs are verified on the IC with different high-resolution modules, including a delay-line based design achieving 9-b resolution at f_s =4 MHz and a counter-based design achieving 8-b resolution at f_s = 586 kHz.