DocumentCode
3810458
Title
Characterization of Equalized and Repeated Interconnects for NoC Applications
Author
Byungsub Kim;Vladimir Stojanović
Author_Institution
Massachusetts Institute of Technology
Volume
25
Issue
5
fYear
2008
Abstract
As the number of cores increases and onand off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem.
Keywords
"Network-on-a-chip","Integrated circuit interconnections","Delay","LAN interconnection","Energy efficiency","Network topology","Multicore processing","Bandwidth","Wire","Constraint optimization"
Journal_Title
IEEE Design & Test of Computers
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2008.137
Filename
4648423
Link To Document