DocumentCode
381369
Title
PLX: a fully subword-parallel instruction set architecture for fast scalable multimedia processing
Author
Lee, Ruby B. ; Fiskiran, A. Murat
Author_Institution
Archit. Lab. for Multimedia & Security, Princeton Univ., NJ, USA
Volume
2
fYear
2002
fDate
2002
Firstpage
117
Abstract
PLX is a small, fully subword-parallel instruction set architecture (ISA) designed for very fast multimedia processing, especially in constrained environments requiring low cost and power, such as handheld multimedia information appliances. In PLX, we select the most useful multimedia instructions added previously to microprocessors. We also introduce a few novel features: a new definition of predication requiring very few bits in each predicated instruction, and datapath scalability from 32-bit to 128-bit words, which allows different degrees of subword parallelism without any changes to the ISA. Performance results from basic multimedia kernels testify to PLX´s superiority for multimedia processing.
Keywords
instruction sets; microprocessor chips; multimedia computing; parallel architectures; program processors; datapath scalability; handheld appliances; information appliances; instruction set architecture; microprocessors; multimedia instructions; multimedia kernels; multimedia processing; predication; subword parallelism; Costs; Home appliances; Information security; Instruction sets; Kernel; Microprocessors; Parallel processing; Registers; Scalability; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo, 2002. ICME '02. Proceedings. 2002 IEEE International Conference on
Print_ISBN
0-7803-7304-9
Type
conf
DOI
10.1109/ICME.2002.1035526
Filename
1035526
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