8 Gb/s CMOS compatible monolithically integrated silicon optical receiver

Author

Csutak, Sebastian M. ; Schaub, Jeremy D. ; Wu, Wei E. ; Campbell, Joe C.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

2002

fDate

17-22 Mar 2002

Firstpage

585

Lastpage

586

Abstract

We have presented a high-speed monolithically integrated optical receiver fabricated in an unmodified 130 nm CMOS process. The receiver operated with BER<10^-9 up to 8 Gb/s with a sensitivity of -10.9 dBm at 5 Gb/s and -15.4 dBm at 3.125 Gb/s. Single voltage supply (3 V) was possible up to 3.125 Gb/s and at 5 V up to 5 Gb/s. Deeper electrodes can improve performance of the photodetector reducing the reverse bias necessary for high sensitivity high speed operation. This is the highest speed operation reported for any Si-based optical receiver.

Keywords

CMOS integrated circuits; electrodes; error statistics; integrated optoelectronics; optical receivers; photodetectors; sensitivity; silicon; 130 nm; 3 V; 3.125 Gbit/s; 5 Gbit/s; 5 V; 8 Gbit/s; CMOS process; Gb/s CMOS compatible monolithically integrated silicon optical receiver; Si; Si-based optical receiver; deeper electrodes; high sensitivity high speed operation; high-speed monolithically integrated optical receiver; photodetector; reverse bias; sensitivity; single voltage supply; Absorption; CMOS process; CMOS technology; Electrodes; Fingers; Local area networks; Optical receivers; PIN photodiodes; Photodetectors; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Optical Fiber Communication Conference and Exhibit, 2002. OFC 2002

Print_ISBN

1-55752-701-6

Type

conf

DOI

10.1109/OFC.2002.1036577

Filename

1036577