Title :
Selective optimization of test for embedded flash memory
Abstract :
Testing of embedded flash can be performed cost effectively in a high volume commodity environment assuming a) the chip is designed to support DAT (direct access test) for flash; b) the design supports full structural scan and boundary scan test; c) the tester supports flash memory test and scan test; and d) the tester can run concurrent scan/boundary scan test and memory test to make use of long flash test time.
Keywords :
boundary scan testing; concurrent engineering; flash memories; integrated circuit testing; logic testing; redundancy; DAT; boundary scan test; concurrent scan/boundary scan test; direct access test; embedded flash memory; full structural scan; high volume commodity environment; optimization; test time; Automatic testing; Built-in self-test; Circuit testing; Costs; Flash memory; Logic testing; Packaging; Performance evaluation; Random access memory; Reliability engineering;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041925
