• DocumentCode
    383336
  • Title

    High performance low power VT-wave-pipeline CMOS circuit in PD/SOI technology

  • Author

    Joshi, R.V. ; Yee, F. ; Kim, K. ; Williams, R.Q. ; Chuang, C.T.

  • Author_Institution
    IBM Res. Div., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    2002
  • fDate
    7-10 Oct 2002
  • Firstpage
    128
  • Lastpage
    129
  • Abstract
    Summary form only given. We have presented a VT-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 μm PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce the history effect in floating-body PD/SOI technology.
  • Keywords
    CMOS logic circuits; adders; leakage currents; low-power electronics; pipeline arithmetic; silicon-on-insulator; 0.13 micron; 1.2 V; 64 bit; CLA adder; PD/SOI technology; Si; VT-wave-pipeline technique; carry-look-ahead adder; highly regular dataflow structures; multi-threshold CMOS circuit technique; pseudo-static circuit style; standby leakage; Adders; CMOSFET logic devices; Leakage currents; Pipeline arithmetic; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, IEEE International 2002
  • Print_ISBN
    0-7803-7439-8
  • Type

    conf

  • DOI
    10.1109/SOI.2002.1044447
  • Filename
    1044447
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=383336