DSP and ASIC implementation of a channel filter for a 3G UTRA-TDD system

This paper describes the design, simulation and implementation of a high performance low power pulse-shaping FIR filter. The filter is for an UTRA-TDD transmitter. The pulse-shaping filter was implemented on a DSP and as an ASIC. A performance analysis and comparison using industry standard EDA tools was performed. A proposed reconfigurable pulse-shaping filter architecture for the receiver in the mobile terminal is also presented. This novel architecture can drastically reduce power dissipation dependant on adjacent channel interference. It automatically scales the number of filter coefficients by monitoring the in-band and out-of-band powers. This new filter performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations.