Designing low electro magnetic emissions circuits through clock skew optimization

The increased density of components within a single chip and on boards and the higher operating frequency modes available with new technologies have posed new challenges in the control of electromagnetic emissions (EME). The problem becomes even more important when considering recent regulations, which require emissions not to exceed certain values. In this paper, a new technique to reduce electromagnetic emissions of synchronous digital integrated circuits is presented. In particular, the spectrum envelope of conducted emissions is reduced significantly by properly shaping the power-supply current. For the combinational blocks, a strong reduction of conducted emissions is obtained by appropriate logic synthesis. For the sequential blocks, the reduction is obtained by spreading clock edges, in compliance with functional timing constraints. In both cases, logic synthesis and clock trees must always be tuned for the actual clock frequency. The proposed method has been applied to design a filter and strong attenuation of harmonics in the spectrum of the power supply current has been observed.