Design guidelines for bipolar frequency dividers

In this paper, design of static current mode bipolar frequency dividers is addressed. Design criteria are provided to set bias currents of cascaded stages to achieve a high maximum operating frequency and keep power consumption as low as possible. In particular, bias current of the first stage is found according to speed requirements, while that of subsequent stages is progressively reduced at the minimum value that meets the speed constraint. The design equations are derived from timing analysis of frequency dividers by using simple delay models, and are simple enough to be used in a pencil-and-paper design. The design criteria are applied to the design of a 1/8 frequency divider in a bipolar process whose npn transistor has an f_T of 20 GHz. SPICE simulations agree well with theoretical results.