Euclidean algorithm VLSI implementations

In this paper a novel architecture for implementation of the Euclidean algorithm is presented. It computes the multiplication inverse of a number K for different values of the dimension n (X^-1≡ modulo n). The proposed architecture can be used for the implementation of cryptographic algorithms and reconfigurable arithmetic units. It is proved, in the paper, that the hardware implementation of the proposed architecture achieves improved power consumption and performance. Two different VLSI designs are introduced. The first design is suitable for low power applications while the second for high performance systems. Power consumption and performance estimations of the two introduced designs are presented.