Recursive filters using systolic architectures and switched capacitor techniques

In this paper, the discrete state space recursive filters are implemented in the form of parallel array processors. The state space description permits the straightforward application of systolic architectures to realize recursive filters of 1D and 2D types. We show that the recursivity inherent to the filtering algorithm introduces a latency proportional to the filter order. Moreover, we show that the use of the CTP decomposition technique together with the cylindrical-type structures reduces significantly this latency and improves the computation throughput of these arrays. The processing cells of the systolic array are designed via switched-capacitor techniques.